Aspiring Semiconductor & VLSI Engineer
๐ Namakkal, Tamil Nadu, India
๐ B.E. Electronics and Communication Engineering
๐ผ FOSSEE Intern @ IIT Bombay
Secured prestigious internship at FOSSEE. Working on digital circuit design and SPICE simulations. Contributing to open-source EDA tools development. Gained expertise in eSim software. Part of eSim team at premier institute.
Team Neural Inference SoC selected as Finalist in prestigious 1-TOPS National Chip Tape-Out Program by VLSI Society of India and C-DAC. Provides real-world exposure to chip design and tape-out processes. Recognized among elite teams nationwide for innovative SoC development.
Won Special Prize at SelfE Hackathon 2024 for innovative IoT project. Developed Adaptive Vision smart lighting system. Implemented motion for automated control. Demonstrated exceptional problem-solving skills. Recognized among top performers among 100 +team.
Achieved Top 3rd position on Skillrack competitive programming platform. Consistently solved challenges and data structure problems. Ranked among programmers in the I ECE B.
Successfully completed Digital Circuits certification from NPTEL with elite and TOP 2%.fundamental concepts of digital logic design and Boolean algebra. Gained expertise in combinational and sequential circuit analysis.
I am an aspiring professional in the semiconductor industry, currently pursuing Electronics and Communication Engineering. My interests lie in VLSI design, digital IC development, and semiconductor devices, with a strong foundation in digital logic, circuit design, and hardware description languages (Verilog).
I am passionate about exploring the end-to-end chip design flow, from device physics and circuit analysis to FPGA prototyping and system-level integration. Alongside academics, I actively engage in projects and simulations that strengthen my understanding of semiconductor technologies, low-power architectures, and EDA tools.
My long-term goal is to contribute to innovations in the semiconductor and VLSI industry, particularly in areas such as digital IC design, embedded systems, and next-generation chip technologies.
FOSSEE, IIT Bombay (Remote) | Oct 2025 โ Present (4 months)
Mumbai, Maharashtra, India
FOSSEE, IIT Bombay (Remote) | Sep 2025 โ Oct 2025 (2 months)
Mumbai, Maharashtra, India
NIELIT Calicut | Dec 2025 (1 month)
Kozhikode, Kerala, India ยท On-site
Bachelor of Engineering - Electronics and Communication Engineering
Sri Eshwar College of Engineering | Aug 2024 โ Jul 2028
Higher Secondary (Mathematics & Computer Science)
Holy Angel's Matric Higher Secondary School | 2023 โ 2024 | 95%
NPTEL | Nov 2025
Skills: Digital Designs
FOSSEE | Oct 2025
Research Migration Project
FOSSEE | Oct 2025
Design and Simulation Research Project
FOSSEE | Oct 2025
Simulation with Complementary Clocking
Udemy | Jul 2025
UC-16acb36c-8f28-4564-9fd3-2baeda83b3bc
Udemy | May 2025
UC-ebaae5f9-acb0-489a-bf88-b78e8db145f1
Scaler | Feb 2025
Spoken Tutorial, IIT Bombay | Dec 2024
4049256KT2
Sololearn | Dec 2024
CC-ZCKAZWP6
Designed during VLSI Hackathon using Xilinx Vivado with Verilog-based real-time voting system. Implemented secure digital voting mechanism with multiple candidate selection and result display. Features comprehensive GitHub version control and collaborative development approach.
Developed a responsive personal portfolio website showcasing semiconductor and VLSI engineering expertise. Built with modern HTML5, CSS3, and JavaScript featuring gradient designs, smooth animations, and interactive carousel. Demonstrates web development skills alongside technical engineering background.
Implements an FPGA-based security system that monitors multiple border zones and detects unauthorized intrusions in real time using FSM. Classifies threats into Safe, Alert, and High Alert states with time-based tamper detection mechanism developed in Verilog HDL on Basys-3 FPGA.
Contact Us
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+91 9345802099
pravin.a2024ece@sece.ac.in
www.pravin-portfolio.com
Namakkal, Tamil Nadu, India